1. Field of the Invention
The present invention relates to static semiconductor memory devices, and particularly to a static semiconductor memory device having a test mode for detecting a defective memory cell readily allowing inversion of stored data.
2. Description of the Background Art
FIG. 10 is a block diagram showing an arrangement of a conventional static random access memory (hereinafter referred to as an SRAM).
Referring to FIG. 10, the SRAM has a power supply terminal 31, a ground terminal 32, a clock input terminal 33, a group of address signal input terminals 34, control signal input terminals 35 to 37, and a data input/output terminal 38. An external power supply potential extVcc is externally applied to power supply terminal 31. A ground potential GND is externally applied to ground terminal 32. External power supply potential extVcc and ground potential GND are generally supplied for the SRAM.
A clock signal CLK is externally applied to clock input terminal 33. Address signals A0 to An (where n is an integer greater than zero) are externally applied to group of address signal input terminals 34. A chip select signal /CS, a write enable signal /WE and an output enable signal /OE are externally applied to control signal input terminals 35 to 37, respectively. Data input/output terminal 38 is used for input of write data DI and output of read data DO.
In addition, the SRAM includes: a plurality of (here, assumed to be four for the clarity of description) memory cells MC1 to MC4 arranged in rows and columns; word lines WL1 and WL2 provided corresponding to respective rows; and pairs of bit lines BL1, /BL1 and BL2, /BL2 provided corresponding to respective columns.
Referring to FIG. 11, memory cell MC1 includes load resistors 61 and 62, driver transistors (N channel MOS transistors) 63 and 64, access transistors (N channel MOS transistors) 65 and 66, and storage nodes N1 and N2. Load resistors 61 and 62 are respectively connected between lines for external power supply potential extVcc and storage nodes N1, N2. Driver transistors 63 and 64 are connected between storage nodes N1, N2 and lines for ground potential GND, with respective gates connected to storage nodes N2 and N1. Access transistors 65 and 66 are respectively connected between storage nodes N1, N2 and bit lines BL1, /BL1, with respective gates connected to word line WL1.
Memory cell MC1 is activated when word line WL1 is brought to an H level, of a selection level, for making access transistors 65 and 66 conductive, and inactivated when word line WL1 is brought to an L level of a non-selection level, for making access transistors 65 and 66 non-conductive.
During writing operation, memory cell MC1 is activated, and one of bit lines BL1 and /BL1 is brought to the H level and the other to the L level in accordance with write data DI. Thereby, one of driver transistors 63 and 64 becomes conductive and the other non-conductive, so that the levels of bit lines BL1 and /BL1 are latched at storage nodes N1 and N2. After memory cell MC is inactivated, electric current is supplied for storage nodes N1 and N2 through load resistors 61 and 62 from lines for external power supply potential extVcc, so that levels of storage nodes N1 and N2, that is, write data DI, is retained.
During reading operation, when memory cell MC1 is activated, current flows to the line for ground potential GND through one of driver transistors 63 and 64 which is conductive from one of bit lines BL1 and /BL1 corresponding to the transistor, whereby the bit line attains to the L level. By comparing the levels of bit lines BL1 and /BL1 in this state, data is read from memory cell MC1.
In addition, the SRAM includes: bit line loads 41 to 44 for charging bit lines BL1 to /BL2 to prescribed potentials; equalizers 45 and 46 for equalizing potentials between pairs of bit lines BL1, /BL1 and BL2, /BL2 during reading operation; a pair of data input/output lines IO and /IO; and column selection gates 47 and 48 for connecting pairs of bit lines BL1, /BL1 and BL2, /BL2 and pair of data input/output lines IO and /IO.
Bit line loads 41 to 44 are formed of N channel MOS transistors diode-connected between lines for external power supply potential extVcc and one ends of bit lines BL1 to /BL2, respectively. Equalizers 45 and 46 are respectively connected between bit lines BL1 and /BL1 and between BL2 and /BL2, and formed of P channel MOS transistors with their gates receiving bit line equalize signals /BLEQ.
Column selection gate 47 includes an N channel MOS transistor connected between the other end of bit line BL1 and one end of data input/output line IO, and an N channel MOS transistor connected between the other end of bit line /BL1 and one end of data input/output line /IO, with gates of the N channel MOS transistors connected to one terminal of a column selection line CSL1. Column selection gate 48 includes an N channel MOS transistor connected between the other end of bit line BL2 and one end of data input/output line IO, and an N channel MOS transistor connected between the other end of bit line /BL2 and one end of data input/output line /IO, with gates of the N channel MOS transistors connected to one end of a column selection line CSL2.
The SRAM further includes registers 51 to 54, a row decoder 55, a control circuit 56, a column decoder 57, a write driver 58 and a sense amplifier 59.
Register 51 operates in synchronization with a clock signal CLK externally applied through clock input terminal 33, and latches address signals A0 to An externally applied through the group of address signal input terminals 34 for selectively applying them to row and column decoders 55 and 57. Register 52 operates in synchronization with clock signal CLK, and latches signals /CS, /WE and /OE externally applied through control signal input terminals 35 to 37 for applying them to control circuit 56.
Row decoder 55 raises one of the plurality of word lines WL1 and WL2 to the H level of the selection level, in accordance with address signals A0 to An applied from register 51. Control circuit 56 selects a prescribed operation mode in accordance with signals /CS, /WE and /OE applied from register 52 for controlling whole operation of the SRAM. Column decoder 57 raises one of the plurality of column selection lines CSL1 and CSL2 to the H level of the selection level, in accordance with address signals A0 to An applied from register 51.
Register 53 operates in synchronization with clock signal CLK, and latches write data DI externally applied through data input/output terminal 38 for applying it to write driver 58. Write driver 58 brings one of data input/output lines IO and /IO to the H level and the other to the L level in accordance with write data DI applied from register 53 for writing data DI to a selected memory cell.
Sense amplifier 59 compares levels of data input/output lines IO and /IO and applies data DO to register 54 in accordance with the comparison result. Register 54 operates in synchronization with clock signal CLK and externally outputs read data DO applied from sense amplifier 59 through data input/output terminal 38.
The operation of the SRAM shown in FIG. 10 and 11 will now be described. During writing operation, word line WL1, for example, is raised to the H level of the selection level by row decoder 55, so that memory cells MC1 and MC2 are activated. Thereafter, column selection line CSL1, for example, is raised to the H level of the selection level by column decoder 57 for making column selection gate 47 conductive, whereby activated memory cell MC1 is connected to write driver 58 through the pair of bit lines BL1 and /BL1 and the pair of data input/output lines IO and /IO.
Write driver 58 brings one of the pair of data input/output lines IO and /IO to the H level and the other to the L level in accordance with write data DI applied from register 53 for writing data to memory cell MC1. When word line WL1 and column selection line CSL1 fall to the L level, data is stored in memory cell MC1.
During reading operation, column selection line CSL1, for example, is raised to the H level of the selection level by column decoder 57 for making column selection gate 47 conductive, whereby the pair of bit lines BL1 and /BL1 are connected to sense amplifier 59 through the pair of data input/output lines IO and /IO. Thereafter, bit line equalize signal /BLEQ attains to the L level of an activation level, for making equalizers 45 and 46 conductive, whereby potentials of bit lines BL1, /BL1 and BL2, /BL2 are equalized.
After bit line equalize signal /BLEQ attains to the H level of an inactivation level, for making equalizer 45 and 46 non-conductive, word line WL1, for example, is raised to the H level of the selection level by row decoder 55, so that memory cells MC1 and MC2 are activated. Thus, current flows from one of the pair of bit lines BL1 and /BL1 to memory cell MC1 in accordance with data stored in memory cell MC1 and, responsively, one of the potentials of the pair of data input/output lines IO and /IO decreases. Sense amplifier 59 compares the potentials of the pair of data input/output lines IO and /IO, and applies read data DO to register 54 in accordance with the comparison result. Register 54 externally outputs read data DO through data input/output terminal 38.
For such SRAM, a hold test (a test for determining the ability of holding stored data) is performed under a low temperature environment before shipping. As load resistors 61 and 62 contained in memory cell MC include polysilicon, resistance values of load resistors 61 and 62 increase with decrease in temperature. Thus, under the low temperature environment, amount of current supplied from the line of external power supply potential extVcc to storage nodes N1 and N2 through load resistors 61 and 62 is reduced, thereby reducing stability of memory cell MC. If corresponding word line WL is raised to the H level for reading of data in this state, data in defective memory cell MC, which readily allows inversion of data, is inverted, due to column current flowing into memory cell MC from corresponding bit lines BL and /BL. Then, by comparing write data and read data in each memory cell MC, a defective memory cell which readily allows inversion of data is detected so as to eliminate the SRAM including such defective memory cell.
Such hold test however requires an equipment for the low temperature environment, disadvantageously increasing test cost.
To cope with this problem, as shown in FIG. 12, a method has been proposed in which a line 67 for supplying an internal power supply potential intVcc to memory cell MC and a line 68 for supplying external power supply potential extVcc to the portion other than memory cell MC are separately provided for making internal power supply potential intVcc lower than external power supply potential extVcc during test, so that current supplied for storage nodes N1 and N2 of memory cell MC is reduced and a defective memory cell is detected under an ordinary temperature environment. According to the method, the equipment for the low temperature environment is not required and reduction in test cost is achieved, as the low temperature environment is not necessary.
FIG. 13 is a diagram showing an arrangement of an internal power supply potential generation circuit for generating such internal power supply potential intVcc. Referring to FIG. 13, the internal power supply potential generation circuit includes a voltage-down converter 71 and a P channel MOS transistor 73. Voltage-down converter 71 includes a plurality of (assumed to be three in the figure) N channel MOS transistors 72 connected in series between a line 68 for external power supply potential extVcc and a line 67 for internal power supply potential intVcc. Each N channel MOS transistor 72 has its gate connected to its drain. In other words, each N channel MOS transistor 72 is diode-connected. P channel MOS transistor 73 is connected between line 68 for external power supply potential extVcc and line 67 for internal power supply potential intVcc, with its gate receiving a test signal TE.
During normal operation, test signal TE is brought to the L level of the inactivation level for making P channel MOS transistor 73 conductive, whereby internal power supply potential intVcc is equalized with external power supply potential extVcc. During test, test signal TE is brought to the H level of the activation level for making P channel MOS transistor 73 non-conductive, whereby internal power supply potential intVcc attains to extVcc-3Vth. It is noted that Vth is a threshold voltage of N channel MOS transistor 72.
Thus, external power supply potential extVcc is supplied for memory cell MC during normal operation for stabilizing its operation, whereas down-converted potential extVcc-3Vth is supplied for memory cell MC during test for inverting data in the defective memory cell under the ordinary temperature environment.
FIG. 14 is a circuit diagram showing an arrangement of a test signal generation circuit for generating test signal TE shown in FIG. 13. Referring to FIG. 14, the test signal generation circuit includes P channel MOS transistors 81 and 82, an N channel MOS transistor 83, inverters 84 and 85 and a capacitor 86. MOS transistors 81 and 83 are connected in series between a prescribed terminal (for example control signal input terminal 37) and a line for ground potential GND, with their gates both connected to line 68 for external power supply potential extVcc.
N channel MOS transistor 83 is used as an element with high resistance value for flowing a small amount of current from a node N1 between MOS transistors 81 and 83 to the line for ground potential GND. Inverters 84 and 85 are connected in series between a node N81 and an output node N83 of the test signal generation circuit. P channel MOS transistor 82 is connected between line 68 for external power supply potential extVcc and a node N82 between inverters 84 and 85, with its gate connected to output node N83. Capacitor 86 is connected between output node N83 and the line for ground potential GND.
During normal operation, external power supply potential extVcc or ground potential GND is applied to control signal input terminal 37 as signal /OE. In this case, P channel MOS transistor 81 becomes non-conductive and node N81 attains to the L level, whereby the potential of output node N83, that is, test signal TE, attains to the L level. At the time, P channel MOS transistor 82 becomes conductive and output node N83 is latched at the L level.
During the hold test, a super Vcc potential which is sufficiently higher than external power supply potential extVcc is applied to control signal input terminal 37. Thereby, P channel MOS transistor 81 becomes conductive and node N81 and hence test signal TE both attain to the H level.
In the method described with reference to FIGS. 12 to 14, however, the resistance values of load resistors 61 and 62 for memory cell MC are high and the amount of current flowing to the line for ground potential GND from line 67 for internal power supply potential intVcc is extremely small. As a result, significant time is required for internal power supply potential intVcc to decrease to down-converted potential extVcc-3Vth for stabilization after test signal TE is brought to the H level, thereby disadvantageously increasing time for testing.
Furthermore, external noise may be introduced to terminal 37 of the test signal generation circuit shown in FIG. 14, causing malfunction of the test signal generation circuit.